Non-volatile memory (NVM) has taken a significant role in a variety of applications so that many integrated circuits commonly have at least some non-volatile memory on them. One of the continuing objectives is for that NVM to take up as little space as possible while adding as little manufacturing process complexity as possible. One of the techniques that have developed in order to reduce processing complexity is to have a floating gate NVM cell made from a single layer of polysilicon. This is called a single-poly cell, which is different from that commonly used for NVM. Typically an NVM array uses a floating gate transistor as the NVM cell that has both a floating gate and a control gate, thus requiring two layers of polysilicon in the manufacturing process. Logic on the other hand generally requires only a single layer of polysilicon. Thus, removing the requirement for a second layer of polysilicon for the NVM would often have the effect of simplifying the manufacturing process by requiring only a single layer of polysilicon in making the integrated circuit, a significant simplification of the process.
One of the disadvantages of using the single-poly floating gate transistor for some types of non-volatile storage is that a second transistor, a select transistor, is required for the NVM cell. This has the disadvantageous effect of requiring more area of the integrated circuit for the NVM array.
Thus, there is a need for a single-poly NVM array that requires reduced area.